Appeal No. 96-0908
Application 08/160,118
Auslander discloses a primitive reduced instruction set
machine wherein every primitive instruction takes exactly one
machine cycle, except for accessing storage. The system
architecture has a condition code generating means for
generating condition bits in accordance with the output of the
arithmetic logic unit (ALU) and an expanded condition register
(claim 1). Auslander discloses that a number of condition
bits (status bits) can be set by the ALU, including, as shown
in Table 1(a), a Carry (CA) bit, an Overflow (OV) bit, a
Compares Equal, Zero Value (EQ) bit, and a Logical Greater
Than (LG) bit. Certain condition bits are not altered by
certain instructions, e.g., the Carry bit (CA) "is not altered
by the compare instruction" (col. 9, lines 29-30) and the
divide step (DVS) instruction sets the Carry bit (CA) and
Overflow bit (OV) but does not change the other condition bits
(col. 13, lines 6-11).
Kawata
Kawata discloses a digital data processor which executes
a conditional instruction within a single machine cycle, which
is used in sorting pieces of data. The processor has an ALU.
"The ALU subtracts the input data from the first and second
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