Appeal No. 96-0908
Application 08/160,118
two registers are identified, expressly or impliedly, as part
of the instruction. The specific associations by consecutive
register numbers (e.g., claim 8) or the second register number
having a register number one less than the first register
number (e.g., claim 9) are not found in claims 1 and 13.
For the reasons discussed above, we sustain the
rejections of claims 1-3, 13-15, and 25-39.
(2) Claims 4 and 16
(3) Claims 5 and 17
(4) Claims 6 and 18
Claims 4-6 and 16-18 are directed to setting a particular
status bit (flag bit or condition bit) corresponding to the
output of the arithmetic logic unit (ALU). The claims do not
require that the status bit is the status bit in claim 1 that
controls the conditional store operation. The status bit
could be just one of the status bits in the status register
set by an ordinary instruction. Diefendorff discloses setting
a "greater than" condition bit (status bit) from a comparison
of two operands using unsigned arithmetic (col. 8, lines
63-68). Since Diefendorff is directed to a Z-compare to
determine which pixel is less, it does not disclose other
kinds of comparisons. Auslander discloses that a number of
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