Appeal No. 96-0908
Application 08/160,118
This is a decision on appeal under 35 U.S.C. § 134 from
the final rejection of claims 1-43.
We affirm-in-part.
BACKGROUND
The disclosed invention is directed to a data processing
apparatus wherein the contents of one of two registers is
stored to memory depending upon the state of a status bit in
response to a register pair conditional store instruction.
Claim 1 is reproduced below.
1. A data processing apparatus comprising:
a memory storing data at addressable memory
locations;
an addressing circuit generating memory addresses
for data accesses to said memory;
a data circuit including
a plurality of data registers, each storing a
predetermined number of data bits,
a status register storing at least one type of
status bit, and
an arithmetic logic unit having operand inputs
and an output coupled to said plurality of data
registers; and
an instruction logic circuit connected to said
addressing circuit and said data circuit, said
instruction logic circuit controlling said addressing
circuit and said data circuit in response to a received
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