Appeal No. 96-0908
Application 08/160,118
instruction, said instruction logic circuit controlling
said addressing circuit and said data circuit to store
said predetermined number of data bits stored in a first
data register into a specified address in said memory if
a status bit selected from said at least one type of
status bit has a first state and to store said
predetermined number of data bits stored in a second data
register associated with said first data register into
said specified address in said memory if a status bit
selected from said at least one type of status bit has a
second state in response to a register pair conditional
store instruction.
The examiner relies on the following prior art
references:
Auslander et al. (Auslander) 4,589,087 May 13,
1986
Diefendorff et a. (Diefendorff) 5,268,995 December 7,
1993
(filed November 21,
1990)
Kawata 5,274,777 December 28,
1993
(filed March 29,
1991)
We refer to the Final Rejection (Paper No. 5) (pages
referred to as "FR__") and the Examiner's Answer (Paper
No. 11) (pages referred to as "EA__") for a statement of the
examiner's position and to the Appeal Brief (Paper No. 10)
(pages referred to as "Br__") for a statement of appellants'
arguments thereagainst. The outstanding rejections are:
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