Appeal No. 96-0908
Application 08/160,118
contains two 32-bit fields (D 0 and D 1) representing Z-valuesZ Z
for two currently stored pixels (D0, D1) is retrieved from
register 54 (figures 3 and 4; col. 8, lines 3-10). The
operands are transferred to the graphics adder unit 30, which
performs two 32-bit Z-value comparisons to determine which
value is greater and the two "greater than" results are
encoded as two bits in the mask register 56. The mask bit
values select which portions of the registers 57 and 58 are
stored in register 59 by the multiplexers 60-67 in figure 5 in
response to a merge instruction. "Thus, the final result
operand is stored in register 59 in the register file 34."
Col. 9, lines 64-65.
Diefendorff further discloses (col. 11, lines 22-31):
The mask value produced by the Z-compare
instructions may be used by a pixel merge instruction
which places the pixel result operand into the register
file 34 for later storage by a STORE instruction executed
by the load/store units 25. Alteratively [sic], a
CONDITIONAL-STORE instruction executed by the load/store
units 25 may directly use the mask value to independently
enable the transfer of each byte in the result operand
from the register file 34 to memory 50 or a video frame
buffer (not shown) via the data bus 48. [Emphasis
added.]
Auslander
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