Appeal No. 96-1207
Application No. 08/064,203
layer is both an insulator suitable for floating gate
memory devices as well as an improved tunneling layer.
Neither of these properties have been previously taught
in any prior art I am aware of.
The noted enhancement of electron tunneling is described in
the specification at page 4, lines 29 through 35.
In paragraph 6 of the Exhibit C declaration, declarant
states that:
Mr. Vasche's work at Xicor significantly advanced the
state of the art in the field of non-volatile memories.
He found that low temperature deposited dielectrics,
properly annealed, are better than thermal oxides for
tunneling. For example, as stated in the
specification, beginning at the bottom of page 6, the
inventor discovered that TEOS tunneling oxides formed
in the manner claimed in this case increase the total
charge which can be conducted through a dielectric
layer by at least an order of magnitude while at the
same time providing a dramatic improvement in
processing yields.
Paragraphs 8 and 9 of the Exhibit C declaration are as
follows:
The structure of the tunneling oxide layer
according to the present invention is significantly
different from prior art tunneling oxide layers since
the inventive layer is substantially free of stress and
defects. See page 4 line 23 to page 5, line 4 of the
specification.
More specifically, first with regard to defects,
when the claimed TEOS deposited oxide layer is being
deposited, it does not consume the underlying layer, as
is well known in the art. Thermal oxide, however, as
is also well known, does consume the underlying layer,
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