Appeal No. 96-1247
Application 08/115,662
Deyhimy does not teach using equal signal links between the
adjusting circuits and the logic circuits. The Examiner
states that this design is notoriously well known.
Appellant argues on page 7 of the brief that inde-
pendent claim 1 is directed to an integrated circuit which
comprises "a plurality of logic circuit regions" where each
logic circuit region has "interconnections" which are formed
by a conductive pattern "so that a clock skew of the clock
signal is minimized among" logic circuits in the logic circuit
region. Appellant also points out that claim 1 also specifies
"a plurality of adjusting circuits" between a clock source and
the logic circuit region in order to adjust the amount of
delay of the clock signal. Appellant points out that claim 1
thus provides for clock skew minimization at two levels, at
the logic circuit region level and at the clock source to the
logic circuit region level. Appellant argues that there is
nothing in Deyhimy that would give an incentive to an ordinary
skilled person to mount such a multi-level attack on clock
skew.
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