Appeal No. 96-1247
Application 08/115,662
a plurality of first logic circuits coupled to the output of
the first buffer, each of the first logic circuits receiving
the clock signal with a first delay time." We further note
that the same language is provided for a second logic circuit
region. Therefore, independent claim 14 also requires a
conductive pattern for the first logic circuits that will
provide a clock skew of the clock signal that is minimized.
Appellant argues that Deyhimy fails to teach or suggest using
a conductive pattern to connect a number of delay elements
which provides local and global levels of clock skew
minimization.
The Federal Circuit states that "[t]he mere fact
that the prior art may be modified in the manner suggested by
the Examiner does not make the modification obvious unless the
prior art suggested the desirability of the modification." In
re Fritch, 972 F.2d 1260, 1266 n.14, 23 USPQ2d 1780, 1783-84
n.14 (Fed. Cir. 1992), citing In re Gordon, 733 F.2d 900, 902,
221 USPQ 1125, 1127 (Fed. Cir. 1984).
Turning to Deyhimy, we agree with the Examiner that
Deyhimy's Figure 3 only shows skew adjusting circuits 122-1
8
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