Appeal No. 96-1727
Application 08/130,575
clearly controls transmission of image data from a processor means to the claimed display
side memory represented by VRAM 104. The processing occurs in units of the broadly
defined predetermined rasters, to the extent claimed, as depicted in the data blocks R1
and R2 in prior art Figure 2. In accordance with the discussion bridging columns 1 and 2
of Nishi, the color processing would entail the teaching corresponding to the claimed
encoder means.
Even with respect to both the Figure 3 and Figure 20 embodiments of Nishi’s own
teachings, the claimed processor side memory of claim 1 may comprise the memory 3
where the processor means recited comprises the CPU 2. In Nishi’s Figure 3 the VRAM
clearly stores information transmitted to it from the CPU through the VDP 1. It is this
VDP 1 that comprises the claimed control means which controls the transmission of image
data from the processor means CPU 102 in Figure 3 of Nishi so that image data are
transmitted for each unit of predetermined rasters to display side memory VRAM 4.
Again, the context of the whole disclosure of Nishi is to process data blocks in a manner
similar to the data blocks for image presentation depicted in prior art Figure 2 as
represented in succeeding figures. Some of the details of identifying the addressability of
each of these blocks relate to Figures 4 through 7 of Nishi. See also Figures 11, 12, and
14. In accordance with Figure 3 the details of the control means may further comprise the
command processing circuit 15 and the image and data processing circuit 10, whereas
4
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