Appeal No. 96-1727
Application 08/130,575
the claimed encoder means may comprise the color palette circuit 12 which encodes for
color presentation bit data supplied to it from the VRAM 4 to form display signals to be
imparted to the CRT 5, which unit again displays the data in the claimed "units of
predetermined rasters."
The Figure 20 version, as principally relied upon by the examiner, may additionally
be construed to teach that the VRAM 4 and the extended VRAM memory 80 may
comprise the display side memory. The claimed processor side memory of claim 1 is not
recited in such a manner as to exclude the external supply memory 3 as comprising this
memory for purposes of this claim. It is further noted that with respect to the admitted prior
art discussion of Figures 1 and 2 as discussed at the top of column 2 of Nishi, it was
known in the art that the VRAM may also be extended by an additional memory device in
the manner depicted with respect to Figure 20.
As to claim 4, the original memory 3 in the Figure 3 version of the embodiments in
Nishi reads upon the claimed external storage means of the preamble of claim 4 and the
CRT 5 remains the display monitor means of this claim. The first memory means
comprises alternatively the VRAM 4 and the extended VRAM memory 80 of the Figure 20
embodiment whereas these same memories, because of their functional usages with
respect to the Figure 20 embodiment, also may be construed to comprise the second
memory means claimed. The VRAMs 4 and 80 clearly are taught to buffer image data
5
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