Appeal No. 96-1727
Application 08/130,575
transmitted from a source memory 3 in the Figures 3 and 20 embodiments. The claimed
control unit in claim 4 reads upon the CPU 2 which is coupled to this previously recited
external memory 3 and to the VRAMs 4 and 80 as just discussed and the CPU clearly
processes image data stored in the VRAMs 4 and 80. Again, in the context of the
disclosure in Nishi as a whole, the processing occurs in the claimed units of
predetermined rasters such as first introduced in prior art Figure 2 in Nishi. The claimed
image data extension unit performs a decoding function met by the details of the video
data processor 1 including optionally the command processor circuit 15,15a; the image
data processing circuit 10,10a in the Figures 3 and 20 embodiments. These two units
work together to perform the logical operations upon the video data to the extent
necessary in Nishi. As such, they perform the claimed decoding operation as broadly
recited. Because the CPU 2, the command processing circuit 15, and the image data
processing circuit 10 shuttle data in and out of the VRAMs 4 and 80 they may be clearly
construed to store decoded image data that had been operated upon in accordance with
these logical operations at least with respect to element 15 in Nishi. The claimed means
for transmitting data functionally reads upon the functions provided by the image data
processing circuit 10 and the color palette circuit 12, which unit clearly meets the video
encoder unit feature of dependent claim 9 on appeal.
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