Ex parte TSUTSUMI - Page 2




          Appeal No. 1996-1758                                                        
          Application No. 08/358,050                                                  


          nonelected invention.  Claims 2, 5, 15-18, and 20-23 have been              
          canceled.                                                                   
               The claimed invention relates to a single gate thin film               
          transistor which, according to pages 4-7 of Appellant’s                     
          specification, is structured to moderate the electric field                 
          concentration in the vicinity of corner portions of the gate                
          electrode.                                                                  
               Claim 1 is illustrative of the invention and reads as                  
          follows:                                                                    
               1.  A single gate thin film transistor, comprising:                    
               a gate electrode formed on an insulating layer and having              
          opposite sidewalls;                                                         
               a dielectric layer formed on said insulating layer and                 
          covering upper and side surfaces of said gate electrode, said               
          dielectric layer overlying said gate electrode having a                     
          thickness t; and                                                            
               a polycrystalline silicon layer formed on an upper                     
          surface of said dielectric layer, said polycrystalline silicon              
          layer having a channel region formed above said gate electrode              
          and having a pair of impurity regions formed respectively at                
          opposite sides of said channel region, said channel region                  
          having a length equal to or greater than the length of the                  
          gate electrodes, and a shape of said channel region having no               
          corners or edges conforming to a shape of the sidewalls of the              
          gate electrode,                                                             
               an interface between said dielectric layer and said                    
          polycrystalline silicon layer lying in a single plane                       
          throughout a first region beneath said channel region and a                 
          second region extending beyond each said sidewall of said gate              
                                          2                                           





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