Appeal No. 1996-2481 Page 12
Application No. 07/828763
generating a mapping from each logical block
number to the physical block number in which the
logical block number is stored;
receiving a logical block number; and
translating the received logical block number to
a physical block number using the generated mapping.
During patent examination, pending claims must be given their
broadest reasonable interpretation. Limitations from the
specification are not to be read into the claims. In re Van
Geuns, 988 F.2d 1181, 1184, 26 USPQ2d 1057, 1059 (Fed. Cir.
1993); In re Prater, 415 F.2d 1393, 1404, 162 USPQ 541, 550
(CCPA 1969). Giving the claims their broadest reasonable
interpretation, they recite translating a logical block number
to a physical block number.
Hoel discloses that each logical patch has a unique
identifying number which is extracted from the portion of the
address output of the patchified logical page image memory,
i.e., the patchified address. The subfield within the
patchified address, viz., the patch identifier, is the portion
of the output address which specifies a modulus of the common
size of the linear physical patch within the system employing
patchification. The patch identifier is input to a mapping
table. The output of the mapping table is used to specify a
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