Appeal No. 1996-2481 Page 7
Application No. 07/828763
input to the MUX is the address bus 11-2 including the address
bits A(22, 21, ..., 0). The address bus 11-3 includes the
address bits A(15, 14, ..., 4), which are input to a permuter
2. The permuter transforms the address bits A(15, 14, ..., 4)
and outputs the transformed address bits onto an output bus
12. Col. 13, ll. 15-31.
The MUX also receives the address bits A(20, ..., 16) and
A(3, ..., 0), which are combined with the permuted address
bits on the output bus. The address bits selected by the MUX
and the A(23) address bit on line 11-1 are combined onto bus
13 as an input to a map unit 4. The map unit transforms a
logical address input on bus 13 into a real address output on
bus 14. The real address is the mapped address A (23, 22,
T
..., 0). Id. at ll. 31-40. Contrary to the claimed one-to-
one relationship between allocation tables and memory blocks,
the reference discloses only a single memory table, viz., map
unit 4, for all memory blocks of the system. The absence of
the claimed relationship from Hoel negates anticipation.
Therefore, we reverse the rejection of claims 1-3, 13-15, and
42-45 under
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