Appeal No. 1996-2481 Page 6
Application No. 07/828763
table in each block, the allocation table having entries that
indicate an offset of a data region within the block ....”
Claim 45 likewise specifies in pertinent part a “memory being
divided into blocks of memory locations, each block have a
table ....” In short, the claims recite a separate allocation
table for each of a plurality of memory blocks, i.e., a one-
to-one relationship between allocation tables and memory
blocks.
The examiner erred in not addressing the one-to-one
relationship. Comparison of Hoel’s disclosure to the claim
language does not evidence that the reference teaches the
claimed relationship. Hoel discloses an image processor and
page printing system having a logical memory for mapping
images and employing patchification. Col. 5, ll. 14-16. The
system includes a processing unit 1 having a data bus 10, an
address bus 11, and control lines 15. The processing unit has
an address of 24 bits, viz., the address bits A(23, 22, ...,
1, 0), which represents an address space of 16 megabytes.
The address bus includes a high order bit A(23), which
connects on line 11-1 to control a multiplexor (MUX) 3. One
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