Ex parte SANCHEZ - Page 2




          Appeal No. 1996-2947                                                        
          Application 08/203,685                                                      



               Appellant has appealed to the Board from the examiner's                
          final rejection of claims 1 through 9, which constitute all                 
          the claims in the application.                                              


               Claim 1 is reproduced below:                                           
               1.  A high-speed submicron channel metal oxide                         
          semiconductor transistor which exhibits excellent punchthrough              
          characteristics and which is ideal for VLSI circuits, formed                
          on a semiconductor substrate of a first conductivity type                   
          having a first concentration comprising:                                    
               a gate insulating layer formed on said substrate;                      
               an inner gate electrode of a predetermined length and                  
          width formed on said gate insulating layer, said inner gate                 
          electrode including laterally opposite sidewalls along said                 
          width of said inner gate electrode;                                         
               a first punchthrough stop region and a second                          
          punchthrough stop region of a second concentration of said                  
          first conductivity type wherein said second concentration of                
          said first conductivity type is greater than said first                     
          concentration of said first conductivity type, said first                   
          punchthrough stop region and said second punchthrough stop                  
          region disposed in said substrate in alignment with said                    
          laterally opposite sidewalls of said inner gate electrode,                  
          respectively;                                                               
               a first conductive spacer and a second conductive spacer               
          formed on said gate insulating layer over a portion of said                 
          first punchthrough stop region and said second punchthrough                 
          stop region, respectively, said first conductive spacer and                 
          said second conductive spacer adjacent to and in electrical                 
          contact with respective laterally opposite sidewalls of said                
          inner gate electrode, said first conductive spacer and said                 
                                          2                                           





Page:  Previous  1  2  3  4  5  6  Next 

Last modified: November 3, 2007