Appeal No. 1996-3193
Application 08/160,112
The closest we can find to any relevant reasoning by the
Examiner is the following (EA5):
[T]he exemplary embodiments disclosed by Taniguchi are
not limited to only one set of X and Y inputs for only
one absolute value Z, and Taniguchi further suggests the
use of first and second multi-bit input signals (see
column 14, line 43, and column [?][)]. Therefore, it
would have been an obvious modification for one of
ordinary skill in the art to input a series of first and
second multi-bit input signals as suggested by Taniguchi
and obtain a series of absolute values.
This does not particularly address the claim limitations.
An operation on a multi-bit numbers does not suggest
simultaneous operations on a plurality of separate numbers,
adding or subtracting the plurality of differences to a
plurality of running sums of absolute values of the
differences, and then adding the partial sums together. Since
Taniguchi does not disclose a running sum of the absolute
values of the differences clearly some reasoning is needed to
demonstrate the obviousness of a plurality of running sums and
then adding the sums together. The Examiner has made no
argument that it would have been obvious to have a plurality
of circuits in parallel and then to sum the partial sums from
each circuit, or any other argument that would address the
claim limitations. Thus, the Examiner has failed to establish
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