Application No. 08/176,867
transistors 30-32 which have their summed currents mirrored via
current mirrors 34-36, 34-42 and 34-54 into current comparators
18, 20 and 22. Current comparator 18 compares the summed current
with 4 times the current I generated by a single bit difference.
Current comparator 20 compares the summed current with 2 or 6
times I, and current comparator 22 compares the summed current
with 1, 3, 5 or 7 times I. Current comparator 20 uses the output
of current comparator 18 to select comparison with either 2 or 6
times I, and current comparator 22 uses the outputs of both
current comparators 18 and 20 to select comparison with one of 1,
3, 5 or 7 times I. Thus, the three current comparators can detect
8 levels of summed current and, consequently, Hamming distances
from 0 to 7.
Opinion
Appellants have not specifically argued the
patentability of any claim other than claim 1. Accordingly,
claims 2-6, 8, 9, 11 and 14-16 stand or fall with claim 1. In re
Nielson, 816 F.2d 1567, 2 USPQ2d 1525 (Fed. Cir. 1987).
Appellants admit that Clapper shows a full adder using
bipolar transistors but argue that neither Clapper nor Basehore,
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Last modified: November 3, 2007