Appeal No. 97-0266
Application No. 08/176,370
through 34, and 41 through 43 were amended to overcome the
objection. In the Supplemental Examiner's Answer, mailed
October
3, 1995, the examiner allowed claims 18, 19, 32 through 34,
and 41 through 43. Accordingly, the claims which remain
before us on appeal are claims 1, 3 through 17, 20 through 31,
and 35 through 40.
The appellants' invention relates to achieving maximum
throughput of dependent operations in a pipelined
microprocessor. More specifically, a designation location
designator of a result of one instruction is compared to
stored source operand location designators of dependent
instructions. When a match is found, a dependent instruction
is dispatched for execution, thereby maximizing the efficiency
in which the processor determines the availability of the
source operands and provides them to the execution unit
executing the dependent instruction. Claim 1 is illustrative
of the claimed invention, and it reads as follows:
1. In a processor having at least one execution unit
for executing a plurality of instructions to thereby generate
execution results, each instruction specifying an opcode and
being associated with at least one source operand location
designator indicating a storage location of a source operand
2
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