Appeal No. 1997-0278
Application No. 08/367,917
BACKGROUND
The appellant's invention relates to a novel device structure for high voltage tolerant
transistors on a 3.3 volt process. An understanding of the invention can be derived from a
reading of exemplary claim 1, which is reproduced below.
1. A low voltage integrated circuit comprising:
a P- doped substrate material;
a first transistor device having
an N- doped well region in the P- substrate material,
an N+ doped drain terminal region in the N- well region,
an N+ doped source terminal region in the P- substrate material,
and
a gate separated from the source and drain terminal regions by a layer of silicon
dioxide;
a second transistor device having
an N+ doped drain terminal region in the P- substrate material, the N+ doped drain
terminal region joining the N+ doped source terminal region of the first transistor
device,
an N+ doped source terminal region in the P- substrate material,
2
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