Appeal No. 97-0320
Application No. 08/096,261
final rejection was filed on September 8, 1995 and was entered
by the Examiner. A further amendment after final rejection
filed December 8, 1995 was also entered by the Examiner.
The claimed invention relates to a semiconductor memory
device having a redundant circuit and a diagnostic circuit for
carrying out a memory test to detect positions of defective
memory cells. Further included is a defective cell position
storage circuit and an output circuit for converting the
defective cell position information into serial data.
Representative claim 1 is reproduced as follows:
1. A semiconductor memory device, comprising:
a normal memory portion having a memory cell matrix which
is composed of a plurality of memory cells arranged at
intersections of word lines and bit lines;
a redundant circuit means having memory cell arrays and
operably coupled to said normal memory portion for replacing
defective memory cells of said normal memory portion in a form
such that all memory cells connected to the word line or the
bit line to which a defective memory cell is connected are
replaced;
a self-diagnostic circuit means, operably coupled to said
normal memory portion, for testing whether or not all memory
cells operate normally;
a defective cell position storage circuit means, operably
coupled to said self-diagnostic circuit means, for storing a
position of either a word line or a bit line connected to
defective memory cells when said self-diagnostic circuit means
2
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