Appeal No. 1997-1185
Application No. 08/497,845
worst delay time margin (zero nanoseconds of path 215),
determines an optimum delay time to be added to a clock net
leading to a clock
input terminal at a terminal side of the worst case path
(e.g., 4
nanoseconds/2 = 2 nanoseconds), and inserts a delay (217) into
the clock net.
Representative independent claim 1 is reproduced as
follows:
1. A clock wiring designing apparatus for designing
clock wiring of an LSI, PWB or the like, said clock wiring
designing apparatus comprising:
delay analyzing means for evaluating delay time
margins for a plurality of paths;
means for detecting a worst case path having a
worst delay time margin among the delay time margins;
means for calculating a clock skew adjusting
time by determining a difference between a delay time margin;
additional delay time calculating means for
determining an optimum delay time to be added to a clock net
leading to a clock input terminal at a terminal side of the
worst case path within a range of the clock skew adjusting
time; and
3
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