Appeal No. 1997-1185
Application No. 08/497,845
Cir. 1983), cert. denied, 469 U.S. 851 (1984)).
The Examiner states that Hooper discloses a data
processing system for analyzing timing in the synthesis of
logic circuits and uses a multipath delay analysis based on
worst delay path. The Examiner reasons that Hooper is
applicable to clock wiring design and analysis because both
Hooper and Appellant’s invention are directed to signal
propagation in a wiring net or media. The Examiner notes that
Hooper discloses a latch circuit to meet timing performance
but does not explicitly disclose inserting a delay gate as
claimed. The Examiner contends that such a feature is well
known as shown by Hitchcock which uses timing analysis and
timing adjustment to meet circuit performance. This would
motivate those skilled in the art to use
gate delay as a means to improve timing performance because
the
gate delay would provide a delay time to meet clock
synchronization. (Answer-pages 3 and 4.)
Appellant agrees that timing considerations are a
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