Appeal No. 1997-1185
Application No. 08/497,845
means for inserting a delay gate in said clock
net so that the delay time determined by the additional delay
time calculating means is added to the clock net as an
additional clock skew, whereby a total time margin is used
between said worst case path and said secondary worst case
path.
The Examiner relies on the following references:
Hooper 5,168,455 Dec. 1, 1992 (filed Mar. 28,
1991)
Hitchcock, Sr. et al., “Timing Analysis of Computer Hardware”,
IBM J. Res. Develop., Vol. 26, No. 1, pp. 100-105, Jan. 1982
Claims 1 through 19 stand rejected under 35 U.S.C.
§ 103 as being unpatentable over Hooper in view of Hitchcock.
Rather than reiterate the arguments of Appellant and
the Examiner, reference is made to the brief and answer for
the respective details thereof.
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