Appeal No. 1997-1185
Application No. 08/497,845
critical factor in circuit design. But, Appellant argues,
Hooper and Hitchcock are directed to circuit component
selection based on a timing budget and a fixed clock rate.
Both fail to teach adjusting the clock rate. (Brief-pages 5
and 6.) At page 7 of the brief Appellant states:
Like Hooper, this [Hitchcock] is all part of the
layout and selection of circuit components, and is
not related to the establishment of a clock net for
selected components.
The Examiner cites several instances where the
references determine and adjust clock delay, and concludes
that clock rate adjustment is clearly disclosed (answer-page
6). We take issue with this reasoning, adjusting clock delay
is not a clock rate adjustment. Note Appellant’s prior art
Figure 2 with a clock rate of 10 nanoseconds versus Figure 5
showing an improved clock rate of 8 nanoseconds.
Appellant’s independent claim recites “determining a
difference between a delay time margin of a secondary worst
case path and the worst delay time margin;”, (emphasis added)
claim 1, lines 9 and 10. Similar language can be found in
claims 2 and 3,
at lines 9 and 10; claim 6, lines 15 and 16; and claim 7,
7
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