Appeal No. 97-2470 Page 3
Application No. 08/201,817
Claim 1, which is representative for our purposes,
follows:
Claim 1. A bridge circuit adapted to be associated
with first and second bus circuits to transfer
data therebetween comprising:
data buffers for storing data being transferred
between the buses,
a circuit for causing a bus master on the first bus
which has attempted an access of the second bus
through the bridge circuit to retry its access,
circuitry for masking any retry until the second bus
is again available, and
circuitry for providing an interval during which a
bus master on the secondary bus may not gain access
to the second bus after the second bus is
relinquished so that a sequence of retry operations
causing a thrashing condition on the first bus is
not generated.
The reference relied on by the patent examiner in
rejecting the claims follows:
Heil et al. (Heil) 5,418,914 May
23, 1995
(effective filing date Sept. 17, 1991)
Claims 1 through 21 stand rejected under 35 U.S.C.
§ 102(e) as anticipated by Heil. (Examiner’s Answer, ¶ 9.)
Rather than repeat the arguments of the appellants or examiner
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