Appeal No. 97-2470 Page 6
Application No. 08/201,817
generating a busy signal when the second bus is in a busy
state, logic for generating a retry signal, and means for
masking any retry until the second bus is again available.
The examiner concludes the rejection by opining that the
interface module also comprises “the claimed means for
providing an interval (See Fig. 3; especially signals “PRQ_L”,
“PACK_L”, “MC_BUSY_L” and Clock 6-20)". (Id.) Amplifying the
last point, the examiner notes “column 5, line 31 - column 6,
line 8 ‘The applicable MCRETRYL signal is driven low ... Clock
16-20 Processor 22 successfully accesses interface 28.’”
(Id., ¶ 11.) “In these two paragraphs,” asserts the examiner,
Heil discloses the claimed interval providing means. (Id.)
In response, the appellants assert that Heil fails to
show any means for providing an interval as set forth by the
present invention. They add the reference’s timing diagram,
viz., Fig. 3, fails to illustrate any function like that
provided by the timer of the present invention. (Appeal Br.
at 6.) The appellants also submit that Heil does not show the
capability of denying a secondary bus master ownership of the
secondary bus. (Id. at 7-8.)
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