Ex parte SHAH et al. - Page 7




          Appeal No. 97-2470                                         Page 7           
          Application No. 08/201,817                                                  


               Regarding independent claims 1 and 6, we find Heil fails               
          to teach the circuitry for providing an interval as claims.                 
          The  claims recite in pertinent part circuitry for providing                
          an interval during which a bus master on the second bus may                 
          not gain access to the second bus after the second bus is                   
          relinquished so that a sequence of retry operations causing a               
          thrashing condition on the first bus is not generated.  (Spec.              
          at 26, 28.)  Comparison of the claim language to the teaching               
          of Heil  evidences that the reference does not teach the                    
          claimed circuitry for providing an interval.                                


               Heil teaches a retry scheme for eliminating deadlock on a              
          first bus containing transactions directed to a second,                     
          unavailable bus.  Col. 1, ll. 9-11.  An interface circuit                   
          connects the first and second buses.  The interface circuit                 
          includes logic for generating a busy signal when the second                 
          bus                                                                         
          is busy and logic for generating a retry signal when the                    
          interface circuit is addressed by a bus master while the                    
          second bus is busy.  Each bus master includes logic for                     
          receiving the retry signal and relinquishing control of the                 







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