Appeal No. 1997-4120 Page 3
Application No. 08/347,341
Claim 4, which is representative for our purposes,
follows:
4. A computer system comprising:
a plurality of interconnected processors;
a plurality of memories each one associated with
one of said interconnected processors, each having a
common storage area to which each of said processors
have write access;
a plurality of interrupt controllers, each one
associated with one of said processors;
wherein, to synchronize changes in the state of
operation of the processors and/or to handle
processor jobs in a synchronous manner, a data set
is able to be entered into said common storage area
of each of said plurality of memories by the
processor that first reaches a predetermined
synchronization point during execution of a process;
wherein said interrupt controllers detect a
change in said data set, said controllers providing
interrupt signals that are fed to said processors,
through which means, according to an identifier in
the entry in the common storage area, a change in
the state of operation of said processors and/or a
synchronous job processing is able to be initiated;
and
means for indicating to said processors whether
the synchronization of a change in the state of
operation or the synchronization of processor job
[sic] is time-critical or non-time-critical.
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