Appeal No. 1997-4120 Page 11
Application No. 08/347,341
to logical "0", a trigger signal 10 becomes active at logical
"0". The flip-flop 7, in response to the active trigger
signal 10, is preset. This sets the task termination signal
and accordingly the nth line of the signal lines 8 to logical
"1", which also sets the trigger signal 10 to logical "1".
Simultaneously, the status signal at the output terminal Q is
set to logical "0", setting the TEST input terminal of the
first processor 1n also to logical "0", whereby the first
processor 1n resumes its interrupted processing. The same
operation is also performed in the other processor n+1, so
that the processors 1n and 1n+1 are synchronized. Id. at ll.
24-48.
In short, Kametani teaches comparing the contents of the
synchronous register 5 of a given synchronous circuit unit
with data transmitted on the signal lines 8. Collectively,
these data are a data set. The data set, however, does not
reside in a common storage area as claimed. To the contrary,
it resides on the signal lines 8.
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