Appeal No. 1997-4120 Page 9
Application No. 08/347,341
controllers associated with the processors detect the entry
and send interrupt signals to the processors to initiate a
synchronous job or to change the state of operation of the
processors. (Reply Br. at 3.)
Kametani relates to synchronizing processors. Col. 1,
ll. 20-22. Each of a plurality of processors 1n, 1n+1 is
provided with a synchronous circuit unit 2n, 2n+1. The
synchronous circuit units 2n, 2n+1 exchange data through
signal lines 8. The synchronous circuit units 2n, 2n+1 each
include a synchronous register 5 and a determination circuit
6. The synchronous register 5 stores data defining a group of
the processors that perform related tasks. The determination
circuit 6 compares exchanged data with the contents of the
synchronous register 5. Col. 8, ll. 20-45.
Consider an example of establishing synchronization among
processors 1n and 1n+1 where a first processor 1n finishes
its task first. Upon finishing, the first processor 1n
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