Appeal No. 98-1643
Application No. 08/544,582
that single reference in making an anticipation rejection
under 35 U.S.C.
§ 102(b).
With regard to whether the examiner’s reliance is
indicated by Leedy itself, we are of the view that it is. The
embodiment of Fig. 4a shows a tester signal processor for
providing inputs to an integrated circuit under test and for
measuring outputs of the integrated circuit. This would
appear to be not much different than what appellant shows as
the prior art in instant Figures 1 and 2 wherein a main frame
51 has a CPU, 61, therein for supplying the inputs and
measuring outputs to and from the integrated circuit under
test.
The Fig. 14 embodiment of Leedy then indicates that the
tester logic circuits are actually placed on, or in contact
with, the integrated circuit to be tested. However, even in
the Fig. 14 embodiment, there clearly are inputs to, and
measurements from, the integrated circuit under test. Either
the inputs are provided by tester circuit 134 itself, in which
case the tester circuit must receive those inputs from some
other source, or input signals are provided to the circuit
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