Appeal No. 1997-0013
Application No. 08/141,664
address data signal.
Claim 1 is illustrative of the claimed invention, and it
reads as follows:
1. A serial access memory, comprising:
a first memory cell array including a plurality
of memory cells each storing data therein, and a
plurality of first word lines for applying
respective first selection signals to the respective
memory cells;
a second memory cell array including a plurality
of memory cells each storing data therein, and a
plurality of second word lines for applying
respective second selection signals to the respective
memory cells;
a first data register, coupled to the first
memory cell array, for latching the data transferred
from the first memory cell array;
a second data register, coupled to the second
memory cell array, for latching the data transferred
from the second memory cell array;
a first address decoder, connected to the first
memory cell array, for outputting the first
selection signals selectively to the first word
lines, so as to select any of the first word lines in
response to first address data applied to said first
address decoder;
a second address decoder, connected to the
second memory cell array, for outputting the
second selection signals selectively to the second word
lines,
2
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