Appeal No. 1997-0013
Application No. 08/141,664
The referenced portion of Watanabe (column 10, lines
55 through 58) states that “[t]he divided SAM(U) and SAM(L)
correspond to '1' and '0' of the most significant bit (MSB) of
a TAP address, and can transfer data independently from each[2]
other.”
Appellant argues (Reply Brief, page 2) that:
Watanabe does disclose two RAM blocks
transferring data to two SAM blocks
according to the value of the most
significant bit (MSB). However, the
value of the MSB is simply observed
and the SAM block designated for the
transfer is chosen based on the value
of the MSB as it was found . . .
Therefore, the MSB of Watanabe is not
converted to a predetermined bit value . . .
With respect to the referenced teachings of Watanabe,
appellant argues (Reply Brief, page 3) that “Watanabe
separates blocks of data based on the MSB, but does not ‘use’
the MSB for anything but block separation and identification.”
We agree with appellant’s arguments. Watanabe never
converts the most significant bit of any type of address data.
Thus, the obviousness rejection of claims 1, 3, 4, 6, 8, 9,
2Watanabe defines a tap address as “representative of the
position of a new serial cycle after the data transfer”
(column 1, lines 46 and 47).
6
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007