Appeal No. 1997-0013
Application No. 08/141,664
OPINION
The obviousness rejection of claims 1 through 19 is
reversed.
The examiner is of the opinion that Shimizu discloses all
of the claimed structure except for the conversion of the most
significant bit (Answer, pages 3, 4 and 8). The examiner
states (Answer, page 8) that “although Shimizu does not teach
the conversion of the most significant bit, . . . Watanabe
clearly teaches the conversion of the most significant bit as
previously analyzed in the rejection.” The examiner’s
previous analysis of the teachings of Watanabe was that
“Watanabe teaches means for controlling the most significant
bit to convert the input address data to first address data
(0-127) and second address data (128-255); see column 10,
lines 55-58” (Answer, page 4). The examiner concludes
(Answer, pages 4 and 5) that “it would have been obvious to
one of ordinary skill in the art to have used the most
significant bit for transferring the input address data as
taught by Watanabe to the memory device of Shimizu because the
transferring operation with the most significant bit set would
provide high speed processing.”
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