Appeal No. 1997-0013
Application No. 08/141,664
so as to select any of the second word lines in
response to second address data applied to said
second address decoder; and
a control circuit, receiving address data that
includes a most significant bit, the address data
having a first portion which specifies addresses
less than a predetermined address value and a second
portion which specifies addresses equal to or greater
than the predetermined address value, for converting
the most significant bit of the address data to a
predetermined
bit value, applying the first portion of the address
data, including the predetermined bit value, to the
first address decoder as the first address data at a
time that the data is transferred from the first and
second memory cell arrays respectively to the first
and second registers, and simultaneously applying
the second portion of the address data, including
the predetermined bit value, to the second address
decoder as the second address data.
The references relied on by the examiner are:
Shimizu 5,301,162 Apr. 5, 1994
(filed Mar. 23, 1993)
Watanabe et al. (Watanabe) 5,319,603 Jun. 7,
1994
(filed Dec. 24, 1991)
Kaneko et al. (Kaneko) 4-275592 1 Oct. 1,
1992
(published Japanese Kokai Patent Application)
Claims 1, 3, 4, 6, 8, 9, 11 through 13 and 19 stand
rejected under 35 U.S.C. § 103 as being unpatentable over
Shimizu in view of Watanabe.
1A copy of the translation of this reference is attached.
3
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