Appeal No. 1997-0586
Application No. 08/243,559
20, which constitute all the claims in the application.
The disclosed invention relates to a pipelined processor
having a plurality of registers. Jump instructions in such a
processor in the prior art cause a delay in pipeline
processing because the target address for a jump instruction
may not be readily available. The invention creates a jump
instruction which has the target instruction address and a
predicted address as a part of the instruction itself so that
these two addresses are readily available, thus substantially
eliminating the delay of fetching these addresses from
elsewhere in the processor system. Thus, a jump instruction
for this processor includes an opcode, a register specifier
and a memory address specifier. A first address, which is the
target address of a jump instruction, is extracted from said
register specifier. A second address, which is a prediction
of said target address, is extracted from said memory address.
The invention is further illustrated by the following claim.
1. A method of operating a pipelined processor, said
processor having a plurality of registers in a register set,
and having a program counter for counting sequential addresses
in memory, comprising the steps of:
fetching instructions from said sequential addresses
2
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