Appeal No. 1997-0586
Application No. 08/243,559
in memory using said program counter, and decoding said
instructions before executing said instructions,
detecting a jump instruction in the fetched
instructions, said jump instruction including an opcode, a
register specifier and a memory address specifier, and
extracting from said register specifier of said jump
instruction an identification of a first of said registers for
storing a first address which is a target address of said jump
instruction, and extracting from said memory address specifier
of said jump instruction a second address which is a
prediction of said target address; and
prefetching an instruction from said second address
rather than from said sequential addresses, before said jump
instruction is executed and before said first address is
available in said first register.
The references relied on by the Examiner are:
Beckwith et al. (Beckwith) 5,136,696 Aug. 4, 1992
(Filed June 27,
1988)
Johnson 5,136,697 Aug. 4, 1992
(Filed Jun. 06,
1989)
Kane, Gerry (Kane), “MIPS R2000 RISC ARCHITECTURE”, Prentice
Hall, Englewood Cliffs, NJ, 1987, pages 1-1 to 4-11 and A-1 to
1-9.
Claims 1 and 14 stand rejected under 35 U.S.C. § 103 over
Beckwith and Johnson, while 2 to 13 and 15 to 20 stand
rejected over Beckwith, Johnson and Kane.
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