Appeal No. 1997-0586
Application No. 08/243,559
did not teach that an instruction contains a predicted address
within the instruction. However, Johnson et al [sic et al.]
taught that each instruction block contains a plurality of
instructions and instruction fetch information.” [Answer, page
7]. It is clear that Johnson has to go to the cache memory
which contains instruction blocks, and each instruction block
contains a plurality of instructions and instruction fetch
information. Thus, a jump instruction in Johnson does not
have the predicted address as a part of the instruction, but
instead has to go the cache memory to obtain it.
Therefore, we do not sustain the obviousness rejection of
claim 1 and claim 14 over Beckwith and Johnson, as each claim
contains the recitation discussed above.
Claims 2 to 13 and 15 to 20
These claims are rejected over Beckwith, Johnson and
Kane. Each of these claims also contains at least the
recitation discussed above. The Examiner asserts [final
rejection, pages
3 to 4] that Kane “taught that the instructions are of fixed
length” and Kane also shows “an address of the first register
[RD] in which is stored the first address which is the target
8
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 Next
Last modified: November 3, 2007