Appeal No. 1997-2399
Application No. 08/355,104
of arbitration between the two microprocessors for control of
a system bus.
Claim 1 is illustrative of the claimed invention, and it
reads as follows:
1. An apparatus for detecting inconsistencies in
microprocessors in a computer system having a system bus
and memory coupled to the system bus, wherein the memory
includes program instructions, the apparatus comprising:
a first microprocessor coupled to the system bus for
executing the instructions in the memory when said first
processor has control of the system bus;
a second microprocessor coupled to the system bus
for executing the instructions in the memory performed
by said first processor when said second processor has
control of the system bus;
processor control logic coupled to said first
processor and said second processor, said processor
control logic arbitrating control of the system bus
between said first processor and said second processor;
wherein said processor control logic removes said
first processor from control of the system bus when said
first processor begins a write cycle and grants control of
the system bus to said second processor;
wherein said processor control logic returns control
of the system bus from said second processor to said first
processor when said second processor begins said write
cycle, said first processor resuming execution of the
instructions in the memory; and
3
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