Appeal No. 1997-2399
Application No. 08/355,104
error detection logic coupled to said first and
second processors which compares address and data
information generated by each of said processors on said
write cycle when said processor control logic returns
control of the system bus to said first processor, said
logic generating a signal indicative of a match between
said address and data signals of said first and second
processors.
The references relied on by the examiner are:
Ossfeldt 4,099,241 Jul. 4,
1978
Burrage et al. (Burrage) 4,590,549 May
20, 1986
Williams 4,816,990 Mar. 28,
1989
Cutts, Jr. et al. (Cutts) 4,965,717 Oct. 23,
1990
Kimura 5,136,595 Aug. 4,
1992
(filed May 24,
1989)
Best 5,140,680 Aug.
18, 1992
(filed Apr. 13,
1988)
Claims 1 through 7, 11, 13, 15 through 20, 23 and 26
stand rejected under 35 U.S.C. § 103 as being unpatentable
over Kimura.
Claims 8, 9 and 22 stand rejected under 35 U.S.C. § 103
as being unpatentable over Kimura in view of Williams.
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