Ex parte MACIAS-GARZA et al. - Page 7

          Appeal No. 1997-2399                                                        
          Application No. 08/355,104                                                  

          mode microprocessor and executes the instruction (column 1,                 
          30 through 33).  The FRM microprocessor compares the addresses              
          and data generated therein with the addresses and data                      
          generated and outputted onto the buses by the normal mode                   
          microprocessor, and outputs a comparison result (column 1,                  
          lines 39 through 44).  The FRM microprocessor performs the                  
          comparison operation at every bus cycle (column 1, line 53                  
          through 55; column 2, line                                                  
          11 through 19; column 4, lines 1 through 4).                                
               The examiner recognizes (Answer, page 4) that “Kimura                  
          does not explicitly discloses [sic] that each of the                        
          processors have access to and control of the system bus at                  
          different times under control of processor control logic,” but              
          nevertheless concludes that “[i]t would have been obvious to                
          one having ordinary skill in the art to realize that the                    
          redundancy processor accesses the busses after the                          
          transferring of data signals from the normal processor to the               
          memory in order for the redundancy processor to obtain                      
          instruction from the memory.”                                               
               Appellants argue (Brief, pages 6 through 8) that the                   

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