Appeal No. 1997-2439
Application 08/417,701
Claims 1 through 14 have been canceled. Claims 20 through 22 have been objected to as being
dependent upon rejected claims, but the Examiner has indicated that these claims would be allowable if
rewritten in independent form including all of the limitations of claims 16 through 19. Appellants have
indicated on page 2 of the brief, that they are deferring any action on claims 20 through 22 until after
this appeal.
The invention relates to methods and apparatus for interfacing multiple I/O subsystem buses to
a common computer system bus.
Independent claim 16 is reproduced as follows:
16. A computer system, comprising:
a system bus;
a processor connected to said system bus;
a first I/O interface circuit connected to said system bus;
a second I/O interface circuit connected to said system bus;
a first I/O bus connected to said first I/O interface circuit, wherein the first I/O bus has a first set
of fixed addresses associated with said first I/O bus; and
a second I/O bus connected to said second I/O interface circuit, wherein the second I/O bus
has a second set of fixed addresses associated with said second I/O bus, and further wherein the first
set of fixed addresses are the same as the second set of fixed addresses,
wherein said first I/O interface circuit includes (1) means for identifying memory addresses and
I/O addresses assigned to said first I/O bus by the computer system, and (2) means for translating
addresses during accesses to the first set of fixed addresses associated with said first I/O bus from
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