Appeal No. 1997-2439
Application 08/417,701
memory addresses and I/O addresses assigned to said first I/O bus by the computer system into
addresses of the first set of fixed addresses associated with said first I/O bus, and
wherein said second I/O interface circuit includes (1) means for identifying memory addresses
and I/O addresses assigned to said second I/O bus by the computer system, and (2) means for
translating addresses during accesses to the second set of fixed addresses associated with said second
I/O bus from memory addresses and I/O addresses assigned to said second I/O bus by the computer
system into addresses of the second set of fixed addresses associated with said second I/O bus.
The Examiner relies on the following references:
Frieder et al. (Frieder) 4,516,199 May 7, 1985
Johnson 4,947,366 Aug. 7, 1990
Claims 15 through 19 and 23 through 29 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Frieder in view of Johnson.
Rather than reiterate the arguments of Appellants and the Examiner reference is made to the
briefs and answer for the respective details thereof.2
OPINION
We will not sustain the rejection of claims 15 through 19 and 23 through 29 under
35 U.S.C. § 103.
2Appellants filed an appeal brief on July 25, 1996. Appellants filed a reply brief on December
16, 1996. The Examiner mailed a communication on January 14, 1997 stating that the reply brief has
been entered and considered but no further response by the Examiner is deemed necessary.
3
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