Appeal No. 1997-3166
Application No. 08/509,638
§ 1.196(b).
BACKGROUND
The invention is directed to a unit memory cell of a static RAM. Claim 15 is reproduced
below.
15. A unit memory cell of a static RAM comprising:
a flip-flop circuit including first and second inverters, said first inverter including a first driver
transistor and a first load element and said second inverter including a second driver transistor and a
second load element, first and second word transistors connected respectively to said first and second
inverters, wherein a channel pattern for said first driver transistor of said first inverter and a channel
pattern for said second driver transistor of said second inverter are symmetrical about a point, a channel
pattern for said first word transistor and a channel pattern for said second word transistor are
symmetrical about the point;
a channel pattern for said first load element of said first inverter and a channel pattern for said
second load element of said second inverter are asymmetrical; and
a gate pattern for said first load element is different from a gate pattern for said second load
element.
The examiner relies on the following references:
Oldham 4,396,996 Aug. 2, 1983
Nagayoshi et al. (Nagayoshi) 4,570,237 Feb. 11, 1986
Plus et al. (Plus) 4,833,644 May 23, 1989
Ikeda et al. (Ikeda) 4,841,481 Jun. 20, 1989
Kayama 5,241,204 Aug. 31, 1993 (filed Aug. 4, 1992)
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