Appeal No. 1997-3166
Application No. 08/509,638
In regard to the Section 102 rejection over Nagayoshi, appellants argue that there are two
voltage pattern lines running across the memory cell, and that there is no indication “that element 11(b)
is connected to the second load element.” (Reply Brief, page 3.)
However, element 11b (Figure 4) of Nagayoshi is disclosed as being a ground line. As shown
in the schematic diagram of Figure 2, each load transistor Tr3 and Tr4 is at least indirectly connected to
ground. As detailed in column 2, lines 11 through 12 and column 3, lines 37 through 41, the electrical
connections of the physical layout of Fig. 4 are disclosed in “Prior Art” Figure 2. Contrary to
argument, element 11(b) of the reference is connected to at least the “second” load element, since it is
connected to both load elements.
Regarding the arrangement shown in Figure 4 of Nagayoshi, while pattern line 11b clearly runs
across the memory cell, we fail to see how voltage pattern line 11a might be thought to run “across” the
memory cell. Pattern line 11a runs across, at most, structures comprising extensions of the memory
cell. At oral hearing, counsel for appellants could not point to anything in the language of Claim 25 that
sets forth anything different from the disclosure of Nagayoshi. We therefore sustain the rejection of
Claims 25-27 over Nagayoshi.
New Ground of Rejection -- 37 CFR 1.196(b)
We enter the following new ground of rejection against the claims in accordance with
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