Appeal No. 1997-3911
Application 08/368,758
altering unit 6 sends information to the address
controller 14 to cause the address control to address the
correcting content storage unit 2 instead of the ROM 15.
After the correction content stored in the
correcting content storage section 2 is executed,
the address control of the address controller 14 is
returned to the address at which the defective
portion in the ROM 15 designated by the correcting
content is skipped.
Figure 2 shows an embodiment in which the correcting
address storing unit 3 of Figure 1 is implemented as a
register 21 and the correcting content storing unit 2 of
Figure 1 is implemented as part of the RAM 26 (Spec. at 7,
lines 20-25). Furthermore, the leading address of the
correcting content stored in the RAM 26 is latched in the
interruption vector register 23b when the correcting
information is written (Spec. at 8, lines 18-21).
A control flag latch 23a stores a "1" or a "0" to indicate
whether or not correction information has been entered into
register 21 and RAM 26 (Spec. at 8, lines 4-9). If the answer
is yes, the control flag latch closes gate 24 to permit any
subsequently generated coincidence signals 5 to be applied to
the input of interruption control circuit 25, thereby causing
control by the CPU 14 to be moved to the address shown by the
interruption register 23b (Spec. at 8, lines 9-17). The end
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