Appeal No. 1997-3911
Application 08/368,758
of the correcting content stored in the RAM 26 is a jump
instruction for skipping the defective portion of the ROM 15
before returning control from RAM 26 to ROM 15 (Spec. at 8,
lines 26-30). The initialization procedure is depicted by
Figure 3, which is a flow chart showing that
[u]pon initialization after the electronics
apparatus is powered, using the correcting
information stored in the EEPROM 27, the correcting
address is latched in the interruption generating
address register 21 by the initial patch loader
stored in the ROM 15 at step ST1. The leading
address of the correcting content is latched in the
interrupt vector register 23b in step ST2. Further,
the correcting content is written in a predetermined
address of the RAM 26 and the control flag latch 23a
is set to "1" at step ST3. [Spec. at 9, lines 5-
15.]
The claims
Claim 14, the sole independent claims on appeal, reads as
follows:
14. A micro-controller integrated on a single substrate
and in which [sic, including?] a read-only information storage
means for storing firmware, address control means for
performing address control, and input means for inputting
information supplied thereto from a source external to the
substrate, the micro-controller comprising:
random access correcting information storage means
located on the single substrate for receiving correcting
information input thereto from the source external to the
substrate through the input means and storing the correcting
information upon any initialization of the micro-controller,
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