Ex parte SHELL et al. - Page 2




               Appeal No.  1997-3916                                                                                               
               Application No.  08/429,650                                                                                         


                                                          BACKGROUND                                                               

               The appellants' invention relates to a field effect transistor with a self-aligned anti-punchthrough implant        

               channel.  An understanding of the invention can be derived from a reading of exemplary claim 25, which is           

               reproduced as follows:                                                                                              

                       25.  A field effect transistor having an aligned anti-punchthrough buried implant channel,                  
                       comprising:                                                                                                 

                              a semiconductor substrate having a principle surface with device areas and field                     
                       oxide areas thereon;                                                                                        

                              a gate oxide layer on said devices areas composed of thermal oxidation;                              

                              a patterned polysilicon layer forming gate electrodes on said gate oxide layers;                     

                              a buried layer of implanted boron ions in said substrate, below and centered on                      
                       said gate electrode and forming a buried anti-punchthrough implant channel which is                         
                       narrower than said gate electrode;                                                                          

                              lightly doped drain (LDD) regions adjacent to said gate electrode;                                   

                              sidewall spacers on sidewalls of said gate electrode composed of silicon oxide;                      

                              source/drain regions in said device area, formed by implantation and thereby                         
                       having a field effect transistor with said buried anti-punchthrough implant channels under                  
                       and centered on said gate electrode.                                                                        

                       The prior art references of record relied upon by the examiner in rejecting the appealed                    

               claims are:                                                                                                         




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