Appeal No. 1997-4115 Page 3
Application No. 08/325,765
BACKGROUND
The invention at issue in this appeal generates logic for
an output encoded finite state machine (FSM). A conventional
FSM typically employs delay (D) flip-flops to store an encoded
value that indicates the current state of the FSM. An output
decoder generates outputs of the FSM based on the current
state as determined from the value stored by the D flip-flops.
An FSM that uses output flip-flops, i.e., flip-flops
placed at the outputs of the FSM, to encode states of the FSM
is called “an output encoded FSM.” The output encoded FSM
works correctly when each state has a unique combination of
output values. When more than one state has the same
combination of output values, however, the output flip-flops
cannot uniquely identify each state. Additional flip-flops
must be added to the output encoded FSM to allow the unique
identification of each state. By taking advantage of
unspecified output values, i.e., "don't care" values, the
invention reduces the number of flip-flops that need to be
added.
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